Overview: KM416S1120D CMOS SDRAM 1M x 16 SDRAM
512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 1.4 June 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.4 (Jun. 1999) KM416S1120D
Revision History
Revision 1.4 (June, 10th 1999) CMOS SDRAM • AC values of tRCD/tRP/tRAS/tRC are returned to the number of clock cycles. Those can be also converted to ns-unit based values by multiplying the number of clock cycles and clock cycle time of each part together. Accordingly, - Changed tRCD and tRP of KM416S1120D-7/8 each from 18ns to 21ns/20ns - Changed tRC of KM416S1120D-7/8 each from 67ns/68ns to 70ns - Changed tRC of KM416S1120D-6 from 66ns(11CLK) to 60ns (10CLK) • Add KM416S1120D-C(183MHz@CL3) part .For -C part, tRDL=2CLK can be supported which is distingusihed by bucket code "J" Revision 1.3 (April 1999)
• Modified power-up sequence. • Changed ILI from +/- 1uA to +/-10uA. • Changed tSAC and tSHZ of KM416S1120DT-G/F8@CL2 and KM416S1120DT-G/F10@CL3 from 7ns to 6ns. Revision 1.2 (March 1999)
• Removed KM416S1120D-Z (125MHz @ CL2) part. • Supported tRDL=2CLK for -6 part which is distinguished by bucket code "J" . Revision 1.1 (February 1999)
• Changed VDD Condition of KM416S1120D-7/8@CL2 from 3.135V~3.6V to 3.0V~3.6V. • Changed AC characteristics table format. Revision 1.0 (February 1999) - Final
• Changed tRDL of KM416S1120D-6 @ CL3 from 2CLK to 1CLK • Changed tRAS and tRC of KM416S1120D-7 @ CL2 from 6CLK and 8CLK to 5CLK and 7CLK each. • Changed tSAC and tSHZ of KM416S1120D-7 @ CL3 from 6ns to 5.5ns • Changed tOH of KM416S1120D-8/10 from 3ns to 2.5ns • Add KM416S1120D-Z (125MHz @ CL2) • Changed ICC1 of KM416S1120D-7 @ CL2 from 120mA to 110mA Revision 0.0 (November 1998) - Preliminary
• Initial draft -2- Rev. 1.4 (Jun.
