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KM416S1120D - 512K x 16bit x 2 Banks Synchronous DRAM LVTTL

General Description

The KM416S1120D is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs -. CAS Latency ( 2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle (2K/32ms) CMOS SDRAM.

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Datasheet Details

Part number KM416S1120D
Manufacturer Unknown Manufacturer
File Size 1.10 MB
Description 512K x 16bit x 2 Banks Synchronous DRAM LVTTL
Datasheet download datasheet KM416S1120D Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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KM416S1120D CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 1.4 June 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.4 (Jun. 1999) KM416S1120D Revision History Revision 1.4 (June, 10th 1999) CMOS SDRAM • AC values of tRCD/tRP/tRAS/tRC are returned to the number of clock cycles. Those can be also converted to ns-unit based values by multiplying the number of clock cycles and clock cycle time of each part together. Accordingly, - Changed tRCD and tRP of KM416S1120D-7/8 each from 18ns to 21ns/20ns - Changed tRC of KM416S1120D-7/8 each from 67ns/68ns to 70ns - Changed tRC of KM416S1120D-6 from 66ns(11CLK) to 60ns (10CLK) • Add KM416S1120D-C(183MHz@CL3) part .