LZ95G824 Datasheet | Unknown Manufacturer

- - - - - - - - - - C-MOS GATE ARRAY LSI -TOP VIEW- LZ95G824 (1/3) IL22 .. 1 2 3 4 5 6 7 8 9 10 11 12 VDD (+5V) GND 37 38 39 40 41 42 43 44 45 46 47 48 GND VDD (+5V) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 (VDD = +5V) PIN I/O No. 1 2 3 4 5 6 7 8 9 10 11 12 I I I I O - - O O O O O SIGNAL TST1 TST2 VRI TVMD CSYN VDD GND CBLK HD VD HBLK PBLK PIN I/O No. 13 14 15 16 17 18 19 20 21 22 23 24 O I - O I I I I I I O O SIGNAL BCP1 TST3 GND DMCP ACL EEMD SMD1 SMD2 EEUD EENR FCDS FS PIN I/O No. 25 26 27 28 29 30 31 32 33 34 35 36 I I I I O - - O O O O O SIGNAL S1I1 S1I2 S2I1 S2I2 MCK1 VDD GND MCK4 VH1X VH2X V1X V2X PIN I/O No. 37 38 39 40 41 42 43 44 45 46 47 48 O O O O O O - O I I O O SIGNAL V3X V4X OFDX FR FH1 FH2 GND LHA RWI CKI CKO RWO LZ95G824 (2/3) 22 21 39 EENR EEUD OFDX 20 19 18 MCK1 SMD2 SMD1 EEMD MCK4 FR FH1 FH2 RWI VRI LHA RWO 29 32 40 41 42 44 48 45 3 .. VH1X VH2X V1X V2X V3X V4X 33 34 35 36 37 38 INPUT ACL CKI EEMD EENR EEUD RWI S1I1, S1I2 S2I1, S2I2 SMD1, SMD2 TST1-TST3 TVMD VRI OUTPUT BCP1 CBLK CKO CSYN DMCP FCDS FH1, FH2 FR FS HBLK HD LHA MCK1, MCK4 OFDX PBLK RWO V1X-V4X VD VH1X, VH2X ; ; ; ; ; ; ; ; ; ; ; ; AC ON INITIAL STATE SETTING REFERENCE CLOCK ELECTRONIC SHUTTER CONTROL SHUTTER SPEED SETTING SHUTTER SPEED SETTING PHASE ADJUST (FR OUTPUT) PHASE ADJUST (FCDS OUTPUT) PHASE ADJUST (FS OUTPUT) SHUTTER SPEED SETTING TEST TELEVISION MODE SELECT EXTERNAL V RESET CSYN CBLK HD VD HBLK PBLK BCP1 DMCP 46 5 8 9 10 11 12 13 16 ; REF. BLACK LEVEL CLAMP POSITE SIGNAL (AREA SENSOR OUTPUT) ; POSITE BLANKING ; REFERENCE CLOCK ; EIA, CCIR REFERENCE POSITE SYNC ; DUMMY CLAMP CONTINUOUS HORIZONTAL PERIOD (AREA SENSOR OUTPUT) ; FEED SLEW CLAMP (AREA SENSOR OUTPUT) ; ; ; ; ; ; ; ; ; ; ; ; ; AREA SENSOR HORIZONTAL TRANSLATE AREA SENSOR RESET SIGNAL SAMPLING (AREA SENSOR OUTPUT) AREA SENSOR HORIZONTAL TRANSLATE STOP = LOW HORIZONTAL SYNC AREA SENSOR HORIZONTAL LAST GATE PHASE ADJUST (FCDS, FS OUTPUT) AREA SENSOR ELECTRIC...