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PALCE610 - (PALCE610 / PALCE600) EE CMOS High Performance Programmable Array Logic

Datasheet Summary

Description

The PALCE610 is a general purpose PAL device and is functionally and fuse map equivalent to the EP610.

It can accommodate logic functions with up to 20 inputs and 16 outputs.

There are 16 I/O macrocells that can be individually configured to the user’s specifications.

Features

  • facili.

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Datasheet preview – PALCE610

Datasheet Details

Part number PALCE610
Manufacturer ETC
File Size 87.05 KB
Description (PALCE610 / PALCE600) EE CMOS High Performance Programmable Array Logic
Datasheet download datasheet PALCE610 Datasheet
Additional preview pages of the PALCE610 datasheet.

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Full PDF Text Transcription

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USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-15/25 CONNECTION DIAGRAMS Top View SKINNYDIP I/O9 PLCC/LCC CLK1 VCC I I I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I CLK2 12950G-2 VCC EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS s Lattice/Vantis Programmable Array Logic (PAL) architecture s Electrically-erasable CMOS technology providing half power (90 mA ICC) at high speed — -15 = 15-ns tPD — -25 = 25-ns tPD s Sixteen macrocells with configurable I/O architecture s Registered or combinatorial operation s Registers programmable as D, T, J-K, or S-R s Asynchronous clocking via product term or bank register clocking from external pins s Register preload for testability s Power-up reset for initialization s Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages
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