PDM41256 Datasheet | Unknown Manufacturer

256K Static RAM 32K x 8-Bit Features s High-speed access times ’l: 7, 8, 10, 12, and 15 ns Ind’l: 8, 10, 12, and 15 ns s Low power operation (typical) - PDM41256SA Active: 400 m W Standby: 150 m W - PDM41256LA Active: 350 m W Standby: 25 m W s Single +5V (±10%) power supply s TTL-patible inputs and outputs s Packages Plastic SOJ (300 mil) - TSO Plastic TSOP - T 1 2 3 4 5 6 7 8 9 10 11 12 Description The PDM41256 is a high-performance CMOS static RAM organized as 32,768 x 8 bits. This product is produced in Paradigm’s proprietary CMOS technology which offers the designer the highest speed parts. Writing to this device is acplished when the write enable (WE) and the chip enable (CE) inputs are both LOW. Reading is acplished when WE remains HIGH and CE and OE are both LOW. The PDM41256 operates from a single +5V power supply and all the inputs and outputs are fully TTLpatible. The PDM41256 es in two versions, the standard power version PDM41256SA and a low power version the PDM41256LA. The two versions are functionally the same and only differ in their power consumption. The PDM41256 is available in a 28-pin plastic TSOP and a 28-pin 300-mil plastic SOJ. Functional Block Diagram Rev. 2.0 - 7/17/96 3-33 Pin Configurations TSOP SOJ Pin Description Name A14-A0 I/O7-I/O0 OE WE CE VCC VSS Description Address Inputs Data Inputs/Outputs Output Enable Input Write Enable Input Chip Enable Input Power (+5V) Ground Truth Table OE X L X H WE X H L H CE H L L L I/O Hi-Z DOUT DIN Hi-Z MODE Standby Read Write Output Disable NOTE: 1. H = VIH, L = VIL, X = DON’T...