S5933QE - Controller Device Summary

General Description

: When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasasserts FRAME# on the next clock to indicate the last data phase is in progress.

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S5933QE controller device summary by Unknown Manufacturer - Datasheet Preview

Datasheet Details

Part number	S5933QE
Manufacturer	Unknown Manufacturer
File Size	79.69 KB
Description	Controller Device Summary
Datasheet	S5933QE Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com DUPLICATE OF A ORIGINAL DOCUMENT FROM AMCC S5933QE PCI Controller Device Summary www.DataSheet4U.com DUPLICATE OF A ORIGINAL DOCUMENT FROM AMCC S5933 PCI CONTROLLER DEVICE SUMMARY PCI S5933QE Matchmaker Device Summary Revision 2, November 1, 1997 The following are all known device and document variations for the AMCC S5933QE PCI Matchmaker and 1997 device data book. The workarounds described below are factory suggestions and are not to imply the only or all possible solutions. Contact your local Field Application Engineer for new workaround developments. Also contact your FAE for the latest design notes and data book corrections or see the AMCC home page at www.amcc.com.