FEATURES
Totally static 8-bit CPU ROM: 256K x 8-bit RAM: 4K x 8-bit Stack: Up to 128-level deep Operation voltage: 2.4V ~ 5.5V Operation frequency: – 3.0Mhz@2.4V(Min.) – 4.0Mhz@2.7V(Min.) Low Voltage Detector (LVD) Memory interface to ROM, RAM, Flash Memory configuration – Three kinds of bank for program, data and interrupts – 12-bit bank register supports up to 44M bytes – 6 programmable chip-selects with 4 modes – Maximum single device of 16M bytes at CS5 General-Purpose I/O (GPIO) ports – 48 multiplexed CMOS bidirectional bit programmable I/Os – Hardware de-bounce option for Port-A – Bit programmable pull-up for input pins – Bit programmable pull-up/down and open-drain/CMOS for Port-C Programmable Watchdog Timer (WDT) Timer/Counter – Two 8-bit timer, one can be a 16-bit event counter – One 8-bit Base timer with 5 coexistent interrupt time settings Three clocking outputs – Clock sources including Timer0/1, baud rate generator 11 prioritized interrupts with dedicated...
