TM50S116T Overview
TM50S116T SDRAM The TM50S116T is organized as 2-bank x 524288-word x 16-bit(1Mx16), fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth,...
TM50S116T Key Features
- CAS Latency (3 or 2 clocks) n Fully synchronous operation referenced
- Burst Length (1,2,4,8 & full page) to clock rising edge
- Burst type (Sequential & Interleave) n Burst read/write and burst read/single write operations capability
- 75 7.5 133.3 5.4 20 Unit ns Mhz ns ns