Unknown Manufacturer WF128K16
This parameter is guaranteed by design but not tested.FEATURES
s Access Times of 50, 60, 70, 90, 120 and 150ns s 40 pin Ceramic DIP (Package 303) s Organized as 128Kx16 and 256Kx16 s Sector Architecture● 8 equal size sectors of 16KBytes each per chip
● Any combination of sectors can be concurrently erased. Also supports full chip erase s 100,000 Erase/Program Cycles Minimum (0°C to 70°C) s Data Retention, 10 Years at 125°C s Commercial, Industrial and Military Temperature Ranges s 5 Volt Programming; 5V ±10% Supply s Low Power CMOS s Embedded Erase and Program Algorithms s TTL Compatible Inputs and CMOS Outputs s Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation s Page Program Operation and Internal Program Control Time * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request. PRELIMINARY * FIG. 1 PIN CONFIGURATION AND BLOCK DIAGRAM TOP VIEW CS2*/NC CS1 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O...