M13S2561616A Datasheet PDF (4M x 16 Bit x 4 Banks Double Data Rate SDRAM) | Download Elite Semiconductor Memory Technology M13S2561616A

M13S2561616A - 4M x 16 Bit x 4 Banks Double Data Rate SDRAM

Description

Pin Name Function Address inputs - Row address A0~A12 - Column address A0~A8 A10/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi-directional Data Strobe.

Features

z z z z z z z z z z z z z z z z z z z z M13S2561616A 4M x 16 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2; 2.5; 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge.

Datasheet Details

Part number	M13S2561616A
Manufacturer	Elite Semiconductor Memory Technology
File Size	753.94 KB
Description	4M x 16 Bit x 4 Banks Double Data Rate SDRAM
Datasheet	M13S2561616A Datasheet

📁 Similar Datasheet

M13S128324A - Double Data Rate SDRAM (ESMT)

M13S5121632A - Double Data Rate SDRAM (ESMT)

M13S64164A-4BG2Y - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)

M13S64164A-4TG2Y - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)

M13S64164A-5BG - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)

M13S64164A-5BG2Y - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)

M13S64164A-5TG - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)

M13S64164A-5TG2Y - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)

M13S64164A-6BG - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)

M13S64164A-6BG2Y - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)

Full PDF Text Transcription

Click to expand full text

www.DataSheet4U.com ESMT Revision History Revision 0.1 (28 Apr. 2006) - Original M13S2561616A Revision 1.0 (07 Jun. 2006) - Delete Preliminary at ever page - Revise typing error of page1 Revision 1.1 (09 May. 2007) - Modify PD, DC specifications and MRS Revision 1.2 (12 Jun. 2007) - Modify tDQSS Revision 1.3 (13 Jul. 2007) - Add -4 speed grade Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.3 1/48 www.DataSheet4U.

Published: Sep 17, 2009 |