M13L128168A
M13L128168A is DDR SDRAM manufactured by EliteMT.
Features z z z z z z z z z z z z z z z z z z z z
2M x 16 Bit x 4 Banks Double Data Rate SDRAM
JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe(DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE LDM/UDM for write masking only VDD = 3.135V-3.83V, VDDQ = 2.375V-2.8V Auto & Self refresh 15.6us refresh interval 1 DQS per byte (LDQS, UDQS) SSTL-2 I/O interface 66pin TSOPII package
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ORDERING INFORMATION:
PRODUCT NO. M13L128168A-3.6T M13L128168A-4T M13L128168A-5T M13L128168A-6T MAX. FREQ 276MHz 250MHz 200MHz 166MHz 3.3V TSOP II VDD PACKAGE
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2003 Revision : 1.3 2/48
ESMT
Functional Block Diagram
CLK CLK CKE Address
Mode Register & Extended Mode Register
Clock Generator
Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter
Bank A
Sense Amplifier Control Logic
CS RAS CAS WE mand Decoder
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Refresh Counter
Column Decoder
CLK, CLK
Pin Arrangement x16
VDD DQ 0 VDDQ DQ 1 DQ 2 VSSQ DQ 3 DQ 4 VDDQ DQ 5 DQ 6 VSSQ DQ 7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
.. x16
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ 9...
