N2SV6H16FS-6K Overview
These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The device is designed to ply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an...
N2SV6H16FS-6K Key Features
- Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Programmable CAS Latency: 2, 3 P
- Dual Data Mask for byte control (x16) Auto Refresh and Self Refresh 64ms refresh period (4K cycle) JEDEC standard 3.3V P