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D5108AFTA-5B-E - EDD5108AFTA-5B-E

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Elpida Memory

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D5108AFTA-5B-E EDD5108AFTA-5B-E by Elpida Memory - Datasheet Preview — Datasheet preview – D5108AFTA-5B-E

Datasheet Details

Part number	D5108AFTA-5B-E
Manufacturer	Elpida Memory
File Size	563.70 KB
Description	EDD5108AFTA-5B-E
Datasheet	D5108AFTA-5B-E Datasheet
Additional preview pages of the D5108AFTA-5B-E datasheet.

Product details

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture.
Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with DQS.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL.

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Published: Nov 20, 2009 |