EBE10UE8AFSA - 1GB DDR2 SDRAM SO-DIMM

Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 /RAS /CAS /WE /CS0 CKE0 CK0, CK1 /CK0, /CK1 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0, SA1 VDD VDDSPD VREF VSS ODT0 NC Function Address input Row address Column address Auto precharge Bank select address Data input/output Row address st

• Double-data-rate architecture; two data transfers per clock cycle.
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
• Differential clock inputs (CK and /CK).
• DLL aligns DQ and DQS transitions with CK transi.