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EBE20AE4ACWA - 2GB Registered DDR2 SDRAM DIMM

Description

www.DataSheet4U.com Pin name A0 to A13 A10 (AP) Function Address input Row address Column address Auto precharge A0 to A13 A0 to A9, A11 BA0, BA1, BA2 Bank select address DQ0 to DQ63 Data input/output CB0 to CB7 Check

Features

  • Double-data-rate architecture; two data transfers per clock cycle.
  • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
  • Differential clock inputs (CK and /CK).
  • DLL aligns DQ and DQS transitions with CK transi.

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Datasheet Details

Part number EBE20AE4ACWA
Manufacturer Elpida Memory
File Size 268.29 KB
Description 2GB Registered DDR2 SDRAM DIMM
Datasheet download datasheet EBE20AE4ACWA Datasheet
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DATA SHEET www.DataSheet4U.com 2GB Registered DDR2 SDRAM DIMM EBE20AE4ACWA (256M words × 72 bits, 1 Rank) Specifications • Density: 2GB • Organization  256M words × 72 bits, 1 rank • Mounting 18 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.0mm  Lead pitch: 1.0mm  Lead-free (RoHS compliant) • Power supply: VDD = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.) • Eight internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms  Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.
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