EBE21RD4AEFA Datasheet | Elpida Memory

DATA SHEET .. 2GB Registered DDR2 SDRAM DIMM EBE21RD4AEFA (256M words × 72 bits, 2 Ranks) Description The EBE21RD4AEFA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA (µBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (µBGA) on the module board. Note: Do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects. Features - 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.0mm  Lead pitch: 1.0mm  Lead-free - Power supply: VDD, VDDQ = 1.8V ± 0.1V - Data rate: 533Mbps/400Mbps (max.) - SSTL_18 patible I/O - Double-data-rate architecture: two data transfers per clock cycle - Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in capturing data at the receiver - DQS is edge aligned with data for READs; center aligned with data for WRITEs - Differential clock inputs (CK and /CK) - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge; data referenced to both edges of DQS - Four internal banks for concurrent operation (ponents) - Burst length: 4, 8 - /CAS latency (CL): 3, 4, 5 - Auto precharge option for each burst access - Auto refresh and self refresh modes - Average refresh period  7.8µs at 0°C ≤ TC ≤ +85°C  3.9µs at +85°C < TC ≤ +95°C - Posted CAS by programmable additive latency for better mand and data bus efficiency - Off-Chip-Driver...