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EBE52UD6AJUA - 512MB DDR2 SDRAM SO-DIMM

Description

Pin name A0 to A12 A10 (AP) BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0, CK1 /CK0, /CK1 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0, SA1 VDD VDDSPD VREF VSS ODT0, ODT1 NC Function Address input Row address Column address Auto precharge Bank select address Data input/output R

Features

  • Double-data-rate architecture; two data transfers per clock cycle.
  • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
  • Differential clock inputs (CK and /CK).
  • DLL aligns DQ and DQS transitions with CK transi.

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Datasheet Details

Part number EBE52UD6AJUA
Manufacturer Elpida Memory
File Size 330.66 KB
Description 512MB DDR2 SDRAM SO-DIMM
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DATA SHEET www.DataSheet4U.com 512MB DDR2 SDRAM SO-DIMM EBE52UD6AJUA (64M words × 64 bits, 2 Ranks) Specifications • Density: 512MB • Organization  64M words × 64 bits, 2 ranks • Mounting 8 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 200-pin socket type small outline dual in line memory module (SO-DIMM)  PCB height: 30.0mm  Lead pitch: 0.6mm  Lead-free (RoHS compliant) • Power supply: VDD = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.) • Four internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5, 6 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms  Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.
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