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EDJ4216EFBG - 256M words x 16 bits 4G bits DDR3L SDRAM

Download the EDJ4216EFBG datasheet PDF. This datasheet also covers the EDJ4204EFBG variant, as both devices belong to the same 256m words x 16 bits 4g bits ddr3l sdram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Double-data-rate architecture: two data transfers per clock cycle.
  • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
  • Differential clock inputs (CK and /CK).
  • DLL aligns DQ and DQS transitions with CK transi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EDJ4204EFBG-ElpidaMemory.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EDJ4216EFBG
Manufacturer Elpida Memory
File Size 392.78 KB
Description 256M words x 16 bits 4G bits DDR3L SDRAM
Datasheet download datasheet EDJ4216EFBG Datasheet

Full PDF Text Transcription for EDJ4216EFBG (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for EDJ4216EFBG. For precise diagrams, tables, and layout, please refer to the original PDF.

View original datasheet text
COVER PRELIMINARY DATA SHEET 4G bits DDR3L SDRAM EDJ4204EFBG (1024M words × 4 bits) EDJ4208EFBG (512M words × 8 bits) EDJ4216EFBG (256M words × 16 bits) Specifications • Density: 4G bits • Organization — 128M words × 4 bits × 8 banks (EDJ4204EFBG) — 64M words × 8 bits × 8 banks (EDJ4208EFBG) — 32M words × 16 bits × 8 banks (EDJ4216EFBG) • Package — 78-ball FBGA (EDJ4204EFBG, EDJ4208EFBG) — 96-ball FBGA (EDJ4216EFBG) — Lead-free (RoHS compliant) and Halogen-free • Power supply: 1.35V (typ) — VDD = 1.283V to 1.45V — Backward compatible for VDD, VDDQ = 1.5V ± 0.