EDS2504APTA
Description
The EDS2504AP is a 256M bits SDRAM organized as 16,777,216 words × 4 bits × 4 banks.
Key Features
- 3.3V power supply Clock frequency: 133MHz (max.) LVTTL interface Single pulsed /RAS 4 banks can operate simultaneously and independently
- Burst read/write operation and burst read/single write operation capability
- Programmable burst length (BL): 1, 2, 4, 8, full page
- 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8) Interleave (BL = 1, 2, 4, 8)
- Programmable /CAS latency (CL): 2, 3
- Refresh cycles: 8192 refresh cycles/64ms
- 2 variations of refresh Auto refresh Self refresh
