EDS2508APTA-7AL - 256M bits SDRAM

Description

The EDS2504AC/AP is a 256M bits SDRAM organized as 16,777,216 words × 4 bits × 4 banks.

The EDS2508 AC/AP is a 256M bits SDRAM organized as 8,388,608 words × 8 bits × 4 banks.

The EDS2516 AC/AP is a 256M bits SDRAM organized as 4194304 words × 16 bits × 4 banks.

Features

3.3V power supply Clock frequency: 133MHz (max. ) LVTTL interface Single pulsed /RAS 4 banks can operate simultaneously and independently.
Burst read/write operation and burst read/single write operation capability.
Programmable burst length.
(BL): 1, 2, 4, 8.
2 variations of burst sequence  Sequential (BL = 1, 2, 4, 8)  Interleave (BL = 1, 2, 4, 8).
Programmable /CAS latency (CL): 2, 3.
Byte cont.

Elpida Memory

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Datasheet Details

Part number	EDS2508APTA-7AL
Manufacturer	Elpida Memory
File Size	559.75 KB
Description	256M bits SDRAM
Datasheet	EDS2508APTA-7AL Datasheet
Additional preview pages of the EDS2508APTA-7AL datasheet.

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Full PDF Text Transcription

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DATA SHEET 256M bits SDRAM EDS2504ACTA, EDS2504APTA (64M words × 4 bits) EDS2508ACTA, EDS2508APTA (32M words × 8 bits) EDS2516ACTA, EDS2516APTA (16M words × 16 bits) Description The EDS2504AC/AP is a 256M bits SDRAM organized as 16,777,216 words × 4 bits × 4 banks. The EDS2508 AC/AP is a 256M bits SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDS2516 AC/AP is a 256M bits SDRAM organized as 4194304 words × 16 bits × 4 banks. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP (II). Pin Configurations /xxx indicates active low signal.

Published: Apr 23, 2005 |