HM5257805B-75 Overview
The HM5257165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5257805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5257405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank.
HM5257805B-75 Key Features
- Programmable CAS latency: 2/3
- Byte control by DQM : DQM (HM5257805B/HM5257405B) : DQMU/DQML (HM5257165B)
- Refresh cycles: 8192 refresh cycles/64 ms
- 2 variations of refresh Auto refresh Self refresh
- Temperature range: 0 to 60°C