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DD2508AETA - EDD2508AETA

Datasheet Summary

Features

  • Double-data-rate architecture; two data transfers per clock cycle.
  • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture.
  • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver.
  • Data inputs, outputs, and DM are synchronized with DQS.
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
  • Differential clock inputs (CK and /CK).
  • DLL.

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Datasheet Details

Part number DD2508AETA
Manufacturer Elpida
File Size 648.64 KB
Description EDD2508AETA
Datasheet download datasheet DD2508AETA Datasheet
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    DATA SHEET 256M bits DDR SDRAM EDD2508AETA (32M words × 8 bits) EDD2516AETA (16M words × 16 bits) Specifications • Density: 256M bits • Organization  8M words × 8 bits × 4 banks (EDD2508AETA) www.DataSheet4U.com  4M words × 16 bits × 4 banks (EDD2516AETA) • Package: 66-pin plastic TSOP (II)  Lead-free (RoHS compliant) • Power supply:  DDR400: VDD, VDDQ = 2.6V ± 0.1V  DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 400Mbps/333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT):  Sequential (2, 4, 8)  Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.
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