Datasheet Details
| Part number | UPD4516161D |
|---|---|
| Manufacturer | Elpida |
| File Size | 442.43 KB |
| Description | 16M Bit Synchronous DRAM |
| Datasheet |
 UPD4516161D Datasheet
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General Description
The µPD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as 524,288 words × 16 bits × 2 banks respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
Key Features
- Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge.
- Pulsed interface.
- Possible to assert random column address in every cycle.
- Dual internal banks controlled by A11.
- Byte control by LDQM and UDQM.
- Programmable Wrap sequence: Sequential / Interleave.
- Programmable burst length: 1, 2, 4, 8 and full page.
- /CAS latency: 3.
- CBR (Auto) refresh and self refresh.
- ×16 organization.