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EMD28164PA - 8M x 16 Mobile DDR SDRAM

Datasheet Summary

Description

This EMD28164PA is 134,217,728 bits synchronous double data rate Dynamic RAM.

Each 33,554,432 bits bank is organized as 4,096 rows by 512 columns by 16 bits, fabricated with EMLSI’s high performance CMOS technology.

This device uses a double data rate architecture to achieve highspeed operation.

Features

  • 1.8V power supply, 1.8V I/O power.
  • LVCMOS compatible with multiplexed address.
  • Double-data-rate architecture; two data transfers per clock cycle.
  • Bidirectional data strobe(DQS).
  • Four banks operation.
  • MRS cycle with address key programs.
  • CAS latency (2, 3 & 4).
  • Burst length (2, 4, 8 & 16).
  • Burst type (Sequential & Interleave).
  • Differential clock inputs(CK and /CK).
  • EMRS cycle with address key programs. www. DataSheet4U. com.
  • PASR(P.

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Datasheet preview – EMD28164PA

Datasheet Details

Part number EMD28164PA
Manufacturer Emerging Memory & Logic Solutions
File Size 825.61 KB
Description 8M x 16 Mobile DDR SDRAM
Datasheet download datasheet EMD28164PA Datasheet
Additional preview pages of the EMD28164PA datasheet.

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    Full PDF Text Transcription

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    EMD28164PA 128M: 8M x 16 Mobile DDR SDRAM Document Title 128M: 8M x 16 Mobile DDR SDRAM Revision History Revision No. 0.0 0.1 Date Jun 4, 2007 Nov 8, 2007 History Initial Draft - Table 8 Operating AC Parameter updated for tCKE and tWR - Table 2 Bonding Pad Location and Identification Table deleted www.DataSheet4U.com - Signal names unified to /CK, /CS, /RAS, /CAS, /WE respectively (Ex.) CK#, CK, CKB unified to /CK - Corrected IDD6 value in Table 16 1.0 May 26, 2008 Release - Table 6 DC CHARACTERISTICS updated for IDD3P, IDD3N, IDD6 - Table 8 OPERATING AC PARAMETER updated for tDS, tDH, tQH, tRC Emerging Memory & Logic Solutions Inc.
    Published: |