Datasheet4U Logo Datasheet4U.com

EM428M1644RTA - Double DATA RATE SDRAM

General Description

The EM428M1644RTA is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 134,217,728 bits which organized as 2Meg words x 4 banks by 16 bits.

The 128Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation.

Key Features

  • Internal Double-Date-Rate architecture with 2 Accesses per clock cycle.
  • VDD/VDDQ= 2.5V ±0.2V for (-75 and -6).
  • VDD/VDDQ= 2.6V ±0.1V for (-5 ).
  • 2.5V SSTL-2 compatible I/O.
  • Burst Length (B/L) of 2, 4, 8.
  • 2,2.5,3 Clock read latency.
  • Bi-directional,intermittent data strobe(DQS).
  • All inputs except data and DM are sampled at the positive edge of the system clock.
  • Data Mask (DM) for write data.
  • Sequential & Int.

📥 Download Datasheet

Datasheet Details

Part number EM428M1644RTA
Manufacturer Eorex
File Size 336.15 KB
Description Double DATA RATE SDRAM
Datasheet download datasheet EM428M1644RTA Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
EM4200 128-bit Read Only Low Frequency Contactless Identification EM Microelectronic
EM4205 512 bit Read/Write Multi-purpose Contactless Identification Device EM Microelectronic
EM4222 Read-Only UHF Identification EM Microelectronic
EM4223 Read-only UHF Radio Frequency Identification EM Microelectronic
EM4233SLIC Long range passive CMOS EM Microelectronic

Other Datasheets by Eorex

Part Number Description
EM42AM1684RTC Double DATA RATE SDRAM
EM42BM3284LBA Double DATA RATE SDRAM
EM42CM1684RTA Double DATA RATE SDRAM
EM44CM1688LBA 1Gb Double DATA RATE-2 SDRAM
EM44CM1688LBB 1Gb Double DATA RATE-2 SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
eorex EM428M1644RTA 128Mb (2M×4Bank×16) Double DATA RATE SDRAM Features • Internal Double-Date-Rate architecture with 2 Accesses per clock cycle. • VDD/VDDQ= 2.5V ±0.2V for (-75 and -6) • VDD/VDDQ= 2.6V ±0.1V for (-5 ) • 2.5V SSTL-2 compatible I/O • Burst Length (B/L) of 2, 4, 8 • 2,2.5,3 Clock read latency • Bi-directional,intermittent data strobe(DQS) • All inputs except data and DM are sampled at the positive edge of the system clock.