Internal Double-Date-Rate architecture with twice accesses per clock cycle.
Single 2.5V ±0.2V Power Supply
2.5V SSTL-2 compatible I/O
Burst Length (B/L) of 2, 4, 8
CAS Latency: 3
Bi-directional data strobe (DQS) for input and
output data,
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Revision History
Revision 0.1 (Jan. 2012) - First release.
EM42CM1684RTA
Jan. 2012
www.eorex.com 1/22
EM42CM1684RTA
1Gb (16M×4Bank×16) Double DATA RATE SDRAM
Features
Description
• Internal Double-Date-Rate architecture with twice accesses per clock cycle.
• Single 2.5V ±0.2V Power Supply • 2.