Datasheet Summary
Revision History
Revision 0.1 (Jan. 2012)
- First release.
Jan. 2012
.eorex. 1/22
1Gb (16M×4Bank×16) Double DATA RATE SDRAM
Features
Description
- Internal Double-Date-Rate architecture with twice accesses per clock cycle.
- Single 2.5V ±0.2V Power Supply
- 2.5V SSTL-2 patible I/O
- Burst Length (B/L) of 2, 4, 8
- CAS Latency: 3
- Bi-directional data strobe (DQS) for input and output data, active by both edges
- Data Mask (DM) for write data
- Sequential & Interleaved Burst type available
- Auto precharge option for each burst accesses
- DQS edge-aligned with data for Read cycles
- DQS center-aligned with data for Write cycles
- DLL aligns DQ &...