Datasheet Summary
Revision History
Revision 0.1 (Oct. 2011) -First release.
Revision 0.2 (Apr. 2012)
- Package dimension change
- delete 9 x 10.5 mm2, add 8 x 10.5 mm2.
Apr. 2012
1/39
.eorex.
2Gb (32M×8Bank×8) Double DATA RATE 3 SDRAM
Features
- JEDEC Standard VDD/VDDQ = 1.5V±0.075V.
- All inputs and outputs are patible with SSTL_15 interface.
- Fully differential clock inputs (CK, /CK) operation.
- Eight Banks
- Posted CAS by programmable additive latency
- Bust length: 4 with Burst Chop (BC) and 8.
- CAS Write Latency (CWL): 5, 6, 7, 8
- CAS Latency (CL): 6, 7, 8, 9, 10, 11
- Write Latency (WL) =Read Latency (RL) -1.
- Bi-directional Differential Data Strobe...