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EM47FM0888SBA
4Gb (64M× 8Bank×8) Double DATA RATE 3 low voltage SDRAM
Features
• JEDEC Standard VDD/VDDQ = 1.5V±0.075V
• All inputs and outputs are compatible with SSTL_15
interface. • Fully differential clock inputs (CK, /CK) operation. • Eight Banks • Posted CAS by programmable additive latency • Bust length: 4 with Burst Chop (BC) and 8. • CAS Write Latency (CWL): 5, 6, 7, 8 • CAS Latency (CL): 6, 7, 8, 9, 10, 11 • Write Latency (WL) =Read Latency (RL) -1. • Bi-directional Differential Data Strobe (DQS). • Data inputs on DQS centers when write. • Data outputs on DQS, /DQS edges when read. • On chip DLL align DQ, DQS and /DQS transition
with CK transition. • DM mask write data-in at the both rising and falling
edges of the data strobe.
EM47FM0888SBA Datasheet
