Datasheet4U Logo Datasheet4U.com

EM484M3244VBA - Synchronous DRAM

Download the EM484M3244VBA datasheet PDF (EM488M3244VBA included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for synchronous dram.

Description

The EM488M3244VBA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 32 bits.

All inputs and outputs are synchronized with the positive edge of the clock.

Features

  • EM488M3244VBA 256Mb (2M×4Bank×32) Synchronous DRAM.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EM488M3244VBA_Eorex.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EM484M3244VBA
Manufacturer Eorex
File Size 229.53 KB
Description Synchronous DRAM
Datasheet download datasheet EM484M3244VBA Datasheet

📁 Similar Datasheet

  • EM4 - Electronic Indicator (ETC)
  • EM4 - Tube (ETC)
  • EM4 - Tuning Indicator (Philips)
  • EM4022 - Multi Frequency Contactless Identification Device Anti-Collision compatible (EM Microelectronic - MARIN SA)
  • EM4025 - Read Only Contactless Identification Device with Anticollision (EM Microelectronic - MARIN SA)
  • EM4026 - Read only Contactless Identification Device (EM Microelectronic - MARIN SA)
  • EM4033 - 64-bit Read Only CMOS (EM Microelectronic)
  • EM4034 - 13.56MHz ISO15693 Standard Compliant Contactless RW Identification Device (EM Microelectronic - MARIN SA)
  • EM4035 - 13.56MHz CRYPTO ISO15693 Compliant Contactless Identification Device (EM Microelectronic - MARIN SA)
  • EM4069 - 128-bit Read/Write Contactless Identification (EM Microelectronic)
Other Datasheets by Eorex

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com eorex Features EM488M3244VBA 256Mb (2M×4Bank×32) Synchronous DRAM Description The EM488M3244VBA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL. Available packages: TFBGA-90B(13mmx8mm). • Fully Synchronous to Positive Clock Edge • Single 3.3V ±0.
Published: |