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EM6A9325 - 4M x 32 Low Power SDRAM

Description

Table 1.

Input Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

Features

  • Clock rate: 133/125/100 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode - CAS# Latency: 1, 2 & 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential & Interleave - Burst-Read-Single-Write.
  • Burst stop function.
  • Individual byte controlled by DQM0-3.
  • Auto Refresh and Self Refresh.
  • EM6A9325 Preliminary (Rev 0.4 June/2003).
  • 4096.

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Datasheet Details

Part number EM6A9325
Manufacturer Etron Technology
File Size 600.76 KB
Description 4M x 32 Low Power SDRAM
Datasheet download datasheet EM6A9325 Datasheet
Additional preview pages of the EM6A9325 datasheet.

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Full PDF Text Transcription

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EtronTech Features Clock rate: 133/125/100 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode - CAS# Latency: 1, 2 & 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential & Interleave - Burst-Read-Single-Write • Burst stop function • Individual byte controlled by DQM0-3 • Auto Refresh and Self Refresh • • • • • EM6A9325 Preliminary (Rev 0.4 June/2003) • 4096 refresh cycles/64ms • Single 2.5V power supply • Interface: LVCMOS •Package : 90 ball-FBGA, 11x13mm, Lead Free 4M x 32 Low Power SDRAM (LPSDRAM) Ordering Information Part Number EM6A9325BG-7.
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