EP504 Datasheet | Eureka

FEATURES - SDRAM controller interfaces directly with AHB Bus and user interface. - Built-in arbitration between two access ports. - Second access port allows memory sharing with user logic devices. - Dual write buffer for simultaneous write posting and SDRAM access. - Dedicated read buffer with data width matching. - Early burst termination and CPU master busy on the AHB bus are supported. - Supports AHB bus data width of 8, 16 and 32 bits. - Zero wait state burst data transfer on both AHB interface and SDRAM. - Operates on both discrete SDRAM chips and PC100/133 SDRAM DIMM. - Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes. - Pipeline access allows continuous data transfer without wasted cycle. - Fast page access on row address matching. - Independent row address matching for each of the 4 SDRAM banks. - Programmable memory size: 4, 8, 16 and 32 bits per SDRAM. - Programmable SDRAM access timing parameters. - Automatic refresh generation with programmable refresh intervals. - Optimized for ASIC and PLD implementations, including Excalibur PLD. BLOCK DIAGRAM EP504 Addr AHB Bus AHB Interface Address multiplexor Page hit circuit SDRAM or SDRAM DIMM AHB data buffers Arbiter Pipeline control User Interface Control registers Programmable timers © 2001 by Eureka Technology Inc. 4962 El Camino Real, Los Altos, CA 94022, USA Tel: 1 650 960 3800 Fax: 1 650 960 3805 http://.eurekatech. Eureka Technology EP504 AHB Bus to SDRAM Controller DESCRIPTIONS The AHB bus SDRAM controller provides high speed SDRAM for the system. It features two access ports. One port interfaces directly to the AHB bus and the other access port is optimized for system core logic such as DMA or PCI bus bridge. The EP504 SDRAM controller contains built-in arbitration unit to allow both the AHB CPU and system core logic to share SDRAM access. Rotating priority scheme ensures equal sharing of the memory bandwidth. The SDRAM controller is a high performance SDRAM...