EP520
EP520 is SDRAM Controller manufactured by Eureka.
Features
None Provided with Core Documentation User guide Design File Formats EDIF netlist Constraints File Top520.ucf Verification VHDL or Verilog test bench Instantiation Templates VHDL, Verilog Reference designs & None application notes Additional Items None Simulation Tool Used Model Technology Modelsim™ 5.4b Support Support provided by Eureka Technology
Notes: 1. Assuming all core I/Os are routed off-chip
Eureka Technology, Inc.
4962 El Camino Real, Suite 108 Los Altos, CA 94022 USA Phone: +1 650-960-3800 Fax: +1 650-960-3805 E-Mail: info@eurekatech. URL: .eurekatech.
Features
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- - Supports Virtex™, Virtex™-E, and Spartan™-II FPGAs Supports industry standard SDRAM and PC100 SDRAM DIMM. Supports register mode and non-register mode PC100 SDRAM DIMM. Programmable memory size and data width. Supports industrial standard 16Mbit, 64Mbit, 128Mbit and 256Mbit SDRAMs. Supports burst size of 1 to 8 and full page burst. Supports zero wait state burst data transfer to maximize data bandwidth. Programmable SDRAM access timing parameters. Automatic refresh generation with programmable refresh intervals. Optional Error Correction Code (ECC). Multiple external SDRAM partitions. Supports external data buffer between user device and SDRAM data bus
Applications
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- Networking equipment munication equipment Video systems Image processing equipment Medical equipment Avionics PC peripherals
December 5, 2000
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EP520 SDRAM Controller
Figure 1: EP520 SDRAM Controller Block Diagram
General Description
The EP520 SDRAM controller interfaces between a processor or DMA device with an SDRAM. It performs SDRAM read and write access based on processor or DMA requests. SDRAM timing such as row and column latency, precharge timing, and row access length are automatically handled by the SDRAM controller. All these timing parameters are set by the SDRAM controller on system reset and can be programmed by the user during run time to optimize system...
