EP520 Datasheet PDF (SDRAM Controller)

EP520 - SDRAM Controller

Description

The EP520 SDRAM controller interfaces between a processor or DMA device with an SDRAM.

It performs SDRAM read and write access based on processor or DMA requests.

SDRAM timing such as row and column latency, precharge timing, and row access length are automatically handled by the SDRAM controller.

Features

None Provided with Core Documentation User guide Design File Formats EDIF netlist Constraints File Top520.ucf Verification VHDL or Verilog test bench Instantiation Templates VHDL, Verilog Reference designs & None.

Datasheet Details

Part number	EP520
Manufacturer	Eureka
File Size	84.31 KB
Description	SDRAM Controller
Datasheet	EP520 Datasheet
Additional preview pages of the EP520 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com EP520 SDRAM Controller December 5, 2000 Product Specification AllianceCORE™ Facts Core Speciﬁcs Supported Family Virtex Device Tested V50-6 CLB Slices 287 1 Clock IOBs1 IOBs1 116 Performance (MHz) 91 Xilinx Tools 3.2i Special Features None Provided with Core Documentation User guide Design File Formats EDIF netlist Constraints File Top520.ucf Verification VHDL or Verilog test bench Instantiation Templates VHDL, Verilog Reference designs & None application notes Additional Items None Simulation Tool Used Model Technology Modelsim™ 5.4b Support Support provided by Eureka Technology Notes: 1. Assuming all core I/Os are routed off-chip Eureka Technology, Inc.

Published: Mar 13, 2007 |