XR28V382 Datasheet | Exar

DESCRIPTION The XR28V382 (V382) is a dual Universal Asynchronous Receiver and Transmitter (UART) for the Intel Low Pin Count (LPC) bus interface. This device can replace or supplement a Super I/O device to add additinal serial ports to the system. The V382 UARTs support any 16-bit I/O address supported by the system. The register set is based on the industry standard 16550 UART, so the V382 operates with standard serial port drivers without requiring a custom driver to be installed. The 128 byte Transmit and Receive FIFOs reduce CPU overhead and minimize the chance of buffer overflow and data loss. In addition to the 16550 UART registers, there are also Configuration register set where enhanced features such as the 9-bit (multidrop) mode, Ir DA mode and the Watchdog Timer can be enabled. The V382 is available in a 32-pin QFN package. APPLICATIONS x Industrial and Embedded PCs x Factory Automation and Process Controls x Network Routers x System Board Designs FEATURES x 128 Byte Transmit and Receive FIFO x pliant to LPC 1.1 Specifications x -40°C to +85°C Industrial Temp Operation x Watchdog Timer with WDTOUT# signal x 2 independent UART channels - Programmable I/O mapped base addresses - Data rates up to 3 Mbps - Selectable RX FIFO interrupt trigger levels - Auto RS-485 Half-Duplex Control mode - Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity - Ir DA mode and separate IRTXA# and IRRXA# pins for the first UART channel - 9-bit (Multidrop) mode x External 24MHz/48MHz clock x Single 3.3V Supply Voltage ( ± 10%) x 5V tolerant inputs x 32-QFN package (5mm x 5mm) FIGURE 1. XR28V382 BLOCK DIAGRAM VCC GND P C IR S T # LCLK LFRAME# L A D [3 :0 ] SER IR Q 3.3V ± 10% LPC Bus Interface G lobal C o n fig u ra tio n R e g is te rs Baud R a te G e n e ra to r TX FIFO (Ir DA Encoder) RX FIFO (Ir DA Decoder) Status and C o n tro l R egisters M odem IOs UART Channel A TXA / PS_3F8_IRQA IR TXA# / PS_CO NF_KEY0 RXA IR RXA# R TSA#/PS_C O NF_2E/R S485 D TR...