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N & P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
N‐CH
P‐CH
BVDSS
40V
‐40V
RDSON (MAX.)
22mΩ 50mΩ
ID
33A
‐22A
UIS, Rg 100% Tested Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
VGS
Continuous Drain Current Pulsed Drain Current1
TC = 25 °C TC = 100 °C
Avalanche Current
Avalanche Energy Repetitive Avalanche Energy2
L = 0.1mH, IAS=15A, RG=25Ω(N) L = 0.1mH, IAS=‐10A, RG=25Ω(P)
L = 0.