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EMC04N08F Datasheet Single N-channel Logic Level Enhancement Mode Field Effect Transistor

Manufacturer: Excelliance MOS

Overview: EMC04N08F Single N-Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary:.

Datasheet Details

Part number EMC04N08F
Manufacturer Excelliance MOS
File Size 360.85 KB
Description Single N-Channel Logic Level Enhancement Mode Field Effect Transistor
Datasheet EMC04N08F-ExcellianceMOS.pdf

General Description

: BVDSS 75V RDSON (MAX.) 4.4mΩ ID 86A Single N Channel MOSFET UIS, Rg 100% Tested Pb-Free Lead Plating& Halogen Free ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS Gate-Source Voltage VGS ±30 Continuous Drain Current Pulsed Drain Current1 TC = 25 °C 86 ID TC = 100 °C 54 IDM 200 Avalanche Current IAS 90 Avalanche Energy L = 0.1mH, ID=90A, RG=25Ω EAS 405 Repetitive Avalanche Energy2 L = 0.05mH EAR 202 Power Dissipation TC = 25 °C TC = 100 °C Operating Junction & Storage Temperature Range PD Tj, Tstg 56 22 -55 to 150 100% UIS testing in condition of VD=38V, L=0.1mH, VG=10V, IL=40A, Rated VDS=75V N-CH THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Junction-to-Case RJC 2.2 Junction-to-Ambient RJA 62.5 1Pulse width limited by maximum junction temperature.

2Duty cycle  1% 3Pulsed drain current rating is package limited.

2022/12/19 UNIT V A mJ W °C UNIT °C / W p.1 EMC04N08F ELECTRICAL CHARACTERISTICS (TJ = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current1 Drain-Source On-State Resistance1 Forward Transconductance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) gfs VGS = 0V, ID = 250A VDS = VGS, ID = 250A VDS = 0V, VGS = ±30V VDS = 60V, VGS = 0V VDS = 50V, VGS = 0V, TJ = 125 °C VDS = 10V, VGS = 10V VGS = 10V, ID = 24A VDS = 5V, ID = 24A DYNAMIC 75 V 2.0 3.0 4.0 ±100 nA 1 A 25 86 A 3.9 4.4 mΩ 60 S Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge1,2 Gate-Source Charge1,2 Gate-Drain Charge1,2 Turn-On Delay Time1,2 Rise Time1,2 Turn-Off Delay Time1,2 Fall Time1,2 Ciss Coss Crss Rg Qg Qgs Qgd td(on)

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