Datasheet Details
| Part number | EMDA5N10F |
|---|---|
| Manufacturer | Excelliance MOS |
| File Size | 360.85 KB |
| Description | Single N-Channel Logic Level Enhancement Mode Field Effect Transistor |
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EMDA5N10F Download (PDF)
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| Part number | EMDA5N10F |
|---|---|
| Manufacturer | Excelliance MOS |
| File Size | 360.85 KB |
| Description | Single N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| Download |
EMDA5N10F Download (PDF)
|
|
|
|
: BVDSS 100V RDSON (MAX.) 150mΩ ID 10A Single N Channel MOSFET UIS, Rg 100% Tested Pb-Free Lead Plating & Halogen Free ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL Gate-Source Voltage VGS Continuous Drain Current Pulsed Drain Current1 TC = 25 °C ID TC = 100 °C IDM Avalanche Current IAS Avalanche Energy L = 0.1mH, ID=12A, RG=25Ω EAS Repetitive Avalanche Energy2 L = 0.05mH EAR Power Dissipation TC = 25 °C TC = 100 °C Operating Junction & Storage Temperature Range PD Tj, Tstg EMDA5N10F LIMITS ±20 10 7 40 12 7.2 3.6 27 11 -55 to 150 UNIT V A mJ W °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL Junction-to-Case RJC Junction-to-Ambient RJA 1Pulse width limited by maximum junction temperature.
2Duty cycle 1％ 3Pulsed drain current rating is package limited TYPICAL MAXIMUM 4.5 62.5 UNIT °C / W 2022/12/19 p.1 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS EMDA5N10F LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current1 Drain-Source On-State Resistance1 Forward Transconductance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) gfs VGS = 0V, ID = 250A VDS = VGS, ID = 250A VDS = 0V, VGS = ±20V VDS = 80V, VGS = 0V VDS = 70V, VGS = 0V, TJ = 125 °C VDS = 10V, VGS = 10V VGS = 10V, ID = 10A VGS = 5V, ID = 5A VDS = 5V, ID = 10A DYNAMIC 100 V 1.2 1.8 3.2 ±100 nA 1 A 25 10 A 130 150 mΩ 150 175 8 S Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge1,2 Gate-Source Charge1,2 Gate-Drain Charge1,2 Turn-On Delay Time1,2 Rise Time1,2 Turn-Off Delay Time1,2 Fall Time1,2 Ciss Coss Crss Rg Qg Qgs Qgd td(on) tr td(off) tf VGS = 0V, VDS = 25V, f = 1MHz VGS = 15mV, VDS = 0V, f =
Single N-Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary:.
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