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74125 - Quad 3-STATE Buffer

General Description

This device contains four independent gates each of which performs a non-inverting buffer function.

The outputs have the 3-STATE feature.

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📁 Similar Datasheet

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Other Datasheets by Fairchild (now onsemi)

Part Number Description
7412 Triple 3-Input NAND Gate
74121 Monostable multivibrator
74123 Dual retriggerable monostable multivibrator
74126 Quad 3-STATE Buffer
7412DC Triple 3-Input NAND Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DM74LS125A Quad 3-STATE Buffer August 1986 Revised March 2000 DM74LS125A Quad 3-STATE Buffer General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.