74AC169 Datasheet | Fairchild Semiconductor

Description The AC169 is fully synchronous 4-stage up/down counter. The AC169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock. Features s ICC reduced by 50% s Synchronous counting and loading s Built-In lookahead carry capability s Presettable for programmable operation s Outputs source/sink 24 m A Ordering Code: Order Number 74AC169SC 74AC169SJ 74AC169MTC 74AC169PC Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols .. Connection Diagram IEEE/IEC Pin Descriptions Pin Names CEP CET CP P0- P3 PE U/D Q0- Q3 TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Parallel Data Inputs Parallel Enable Input Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009934 .fairchildsemi. Functional Description The AC169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the remended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is...