74AC648
Description
The AC648 consists of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure 4.
Features s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil slim dual-in-line package s Outputs source/sink 24 m A s Inverted data to output
Ordering Code:
Order Number 74AC648SC 74AC648SPC Package Number M24B N24C Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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