74ACQ646 Datasheet | Fairchild Semiconductor

Description The ACQ/ACTQ646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental handling functions available are illustrated in Figure 1, Figure 2, Figure 3 and Figure 4. The ACQ/ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. Features s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Independent registers for A and B busses s Multiplexed real-time and stored data transfers s 300 mil slim dual-in-line package s Outputs source/sink 24 m A s Faster prop delays than the standard AC/ACT646 Ordering Code: Order Number Package Number Package Description 74ACQ646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACQ464ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTQ646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ464ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names A0- A7 B0- B7 CPAB, CPBA SAB, SBA G DIR Descriptions Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of...