GENERAL DESCRIPTION
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. FEATURES
s ICC reduced by 50% s Ideal for addressable register applications s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s Outputs source/sink 24 mA s See 273 for master reset version s See 373 for transparent latch version s See 374 for 3-STATE version s ACT377 has TTL-compatible inputs Ordering Code: Order Number 74AC377SC 74AC377SJ 74AC377MTC 74AC377PC 74ACT377SC 74ACT377SJ 74ACT377MTC 74ACT377PC Package Number M20B M20D MTC20 N20A M20B M20D MTC20 N20A Package DESCRIPTION
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EI...
Fairchild Semiconductor
