Datasheet4U Logo Datasheet4U.com

74ALS125 - Quad 3-STATE Buffer

General Description

This device contains four independent gates each of which performs a non-inverting buffer function.

The outputs have the 3-STATE feature.

The 3-STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or rampdown.

Key Features

  • s Advanced low power oxide-isolated ion-implanted Schottky TTL process s Functional and pin compatible with the 74LS counterpart s Switching response specified into 500Ω and 50 pF load s Switching response specifications guaranteed over full temperature and VCC supply range s PNP input design reduces input loading s Low level.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74ALS1005 Hex Inverting Drivers AVG
74ALS109A Dual J-K positive edge-triggered flip-flop NXP
74ALS10A Triple 3-Input NAND gate NXP
74ALS112A Dual J-K negative edge-triggered flip-flop NXP
74ALS11A Triple 3-Input AND gate NXP

Other Datasheets by Fairchild (now onsemi)

Part Number Description
74ALS1035 Hex Non-Inverting Driver
74ALS133 13-Input NAND Gate
74ALS169B Synchronous Four-Bit Up/Down Counters
74ALS04B DM74ALS04B
74ALS09 Quad 2-Input AND Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74ALS125 Quad 3-STATE Buffer November 1989 Revised February 2000 DM74ALS125 Quad 3-STATE Buffer General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. The 3-STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or rampdown. This eliminates bus glitching problems that arise during power-up and power-down. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.