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74ALVC16835 - Low Voltage 18-Bit Universal Bus Driver

Datasheet Summary

Description

The ALVC16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs.

Features

  • s Compatible with PC100 DIMM module specifications s 1.65V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (CLK to O n) 4.5 ns max for 3.0V to 3.6V VCC 5.5 ns max for 2.3V to 2.7V VCC 9.2 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model >200V Note 1: To ensure the high-impedance state during power up or power do.

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Datasheet Details

Part number 74ALVC16835
Manufacturer Fairchild Semiconductor
File Size 88.75 KB
Description Low Voltage 18-Bit Universal Bus Driver
Datasheet download datasheet 74ALVC16835 Datasheet
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74ALVC16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs September 2001 Revised February 2002 74ALVC16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs General Description The ALVC16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Ouputs (O n) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled.
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