GENERAL DESCRIPTION
Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories. FEATURES
s Serial or parallel input s Serial or parallel output s Expandable without additional logic s 3-STATE outputs s Fully compatible with all TTL families s Slim 24-pin package s 9423 replacement Ordering Code: Order Number 74F433SPC Package Number N24C Package DESCRIPTION
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Logic Symbol Connection Diagram © 1999 Fairchild Semiconductor Corporation DS009544 74F433 Unit Loading/Fan Out U.L. Pin Names PL CPSI IES TTS MR OES TOP TOS CPSO OE D0–D3 DS Q0–Q3 QS IRF ORE DESCRIPTION
HIGH/LOW Parallel Load Input Serial Input Clock Serial Input Enable Transfer to Stack Input Master Reset Serial Output Enable Transfer Out Parallel Transfer Out Serial Serial Output Clock Output Enable Parallel Data Inputs Serial Data Input Parallel Data Outputs Serial Data Output Input Register Ful...