GENERAL DESCRIPTION
Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The 74F533 is the same as the 74F373, except that the outputs are inverted. FEATURES
s Eight latches in a single package s 3-STATE outputs for bus interfacing s Inverted version of the 74F373 Ordering Code: Order Number 74F533SC 74F533SJ 74F533PC Package Number M20B M20D N20A Package DESCRIPTION
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram © 2000 Fairchild Semiconductor Corporation DS009548 74F533 Unit Loading/Fan Out U.L. Pin Names D0 – D7 LE OE O0–O7 Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) Complementary...
Fairchild Semiconductor
