GENERAL DESCRIPTION
FEATURES
s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74F373 s 3-STATE outputs for bus interfacing s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74F573SC 74F573SJ 74F573PC Package Number M20B M20D N20A Package DESCRIPTION
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009566 74F573 Unit Loading/Fan Out Pin Names D0–D7 LE OE O0–O7 Data Inputs Latch Enable Input (Active HIGH) 3-STATE Output Enable Input (Active LOW) 3-STATE Latch Outputs DESCRIPTION
U.L. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches.
Fairchild Semiconductor
