74LS165 Datasheet PDF - Fairchild Semiconductor 8-Bit Parallel In/Serial Output Shift Registers Specs

74LS165 - 8-Bit Parallel In/Serial Output Shift Registers

Datasheet Summary

Description

This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked.

Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input.

Features

s Complementary outputs s Direct overriding (data) inputs s Gated clock inputs s Parallel-to-serial data conversion s Typical frequency 35 MHz s Typical power dissipation 105 mW Ordering Code: Order Number DM74LS165M DM74LS165WM DM74LS165N Package Number M16A M16B N16E Package.

Datasheet Details

Part number	74LS165
Manufacturer	Fairchild Semiconductor
File Size	73.32 KB
Description	8-Bit Parallel In/Serial Output Shift Registers
Datasheet	74LS165 Datasheet
Additional preview pages of the 74LS165 datasheet.

📁 Similar Datasheet

74LS16 - Hex Inverter Buffers/Drivers (Texas Instruments)

74LS160 - BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS (SYC)

74LS160 - BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS (ON Semiconductor)

74LS160 - Synchronous Decade Counters (Hitachi Semiconductor)

74LS160 - BCD DECADE COUNTERS/4-BIT BINARY COUNTERS (Motorola)

74LS160A - Synchronous Decade Counters (Hitachi Semiconductor)

74LS160A - BCD DECADE COUNTERS/4-BIT BINARY COUNTERS (ON Semiconductor)

74LS160A - BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS (Motorola)

74LS161 - BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS (SYC)

74LS161 - BCD DECADE COUNTERS/4-BIT BINARY COUNTERS (Motorola)

Full PDF Text Transcription

Click to expand full text

DM74LS165 8-Bit Parallel In/Serial Output Shift Registers August 1986 Revised March 2000 DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input.

Published: Apr 23, 2005 |