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74LS503 - 8-Bit Successive Approximation Register

Description

The DM74LS503 register has an active LOW Enable (E) input that is used in cascading two or more packages for longer word lengths.

A HIGH signal on E, after a START operation, forces Q7 HIGH and prevents the device from accepting serial data.

Features

  • Performs serial-to-parallel conversion.
  • Expansion control for longer words.
  • Storage and control for successive approximation A to D conversion.
  • Low power Schottky version of 2503 Ordering Code: Order Number Package Number Package.

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Datasheet preview – 74LS503

Datasheet Details

Part number 74LS503
Manufacturer Fairchild Semiconductor
File Size 122.89 KB
Description 8-Bit Successive Approximation Register
Datasheet download datasheet 74LS503 Datasheet
Additional preview pages of the 74LS503 datasheet.

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Full PDF Text Transcription

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DM74LS503 8-Bit Successive Approximation Register March 1989 Revised March 2000 DM74LS503 8-Bit Successive Approximation Register (with Expansion Control) General Description The DM74LS503 register has an active LOW Enable (E) input that is used in cascading two or more packages for longer word lengths. A HIGH signal on E, after a START operation, forces Q7 HIGH and prevents the device from accepting serial data. With the E input of an DM74LS503 connected to the CC output of a preceding (more significant) device, the DM74LS503 will be inhibited until the preceding device is filled, causing its CC output to go LOW. This LOW signal then enables the DM74LS503 to accept the serial data on subsequent clocks.
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