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74LS85 Datasheet PDF

Fairchild Semiconductor 74LS85

The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the leastsignificant bits must have a high-level voltage applied to the A = B input.
Part No. 74LS85
Datasheet 74LS85 Download
Manufacturer
Fairchild Semiconductor
Description 4-Bit Magnitude Comparator
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74LS85 datasheet page 1 preview

GENERAL DESCRIPTION

These 4-bit magnitude comparators perform comparison of straight binary or BCD codes. Three fully-decoded decisions about two, 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The cascading path is implemented with only a two-gate-level delay to reduce overall comparison times for long words.

FEATURES

s Typical power dissipation 52 mW s Typical delay (4-bit words) 24 ns Ordering Code: Order Number DM74LS85M DM74LS85N Package Number M16A N16E Package

DESCRIPTION

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006379 DM74LS...
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