74LVQ241 Datasheet | Fairchild Semiconductor

74LVQ241 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs April 1998 74LVQ241 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description The LVQ241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. Features n Ideal for low power/low noise 3.3V applications n Implements patented EMI reduction circuitry n Available in SOIC JEDEC, SOIC EIAJ and QSOP packages n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75Ω n 4 k V minimum ESD immunity Ordering Code: Order Number 74LVQ241SC 74LVQ241SJ 74LVQ241QSC Package Number M20B M20D MQA20 Package Description 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC 20-Lead Molded Shrink Small Outline Package, SOIC EIAJ 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Assignment for SOIC and QSOP DS011355-2 DS011355-1 © 1998 Fairchild Semiconductor Corporation DS011355 .fairchildsemi. Truth Tables Inputs OE1 L L H Inputs OE2 L H H H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Outputs In L H X (Pins 12, 14, 16, 18) L H Z Outputs In X H L (Pins 3, 5, 7, 9) Z H L Pin Descriptions Pin Names OE1, OE2 I0- I7 O0- O7 Inputs Outputs Description 3-STATE Output Enable Inputs .fairchildsemi....