Download 74VHC393 Datasheet PDF
Fairchild Semiconductor
74VHC393
74VHC393 is Dual 4-Bit Binary Counter manufactured by Fairchild Semiconductor.
Description The VHC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It contains two independent counter circuits in one package, so that counting or frequency division of 8 binary bits can be achieved with one IC. This device changes state on the negative going transition of the CLOCK pulse. The counter can be reset to “0” (Q0- Q3 = “L”) by a HIGH at the CLEAR input regardless of other inputs. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features s High Speed: f MAX = 170 MHz (typ) at TA = 25°C s Low power dissipation: ICC = 4 µA (max) at TA = 25°C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection is provided on all inputs s Pin and function patible with 74HC393 Ordering Code: Order Number 74VHC393M 74VHC393SJ 74VHC393MTC 74VHC393N Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Pin Names CLR1, CLR2 CP1, CP2 QA, QB, QC, QD Description Clear Inputs Clock Pulse Inputs Outputs © 1999 Fairchild Semiconductor Corporation DS011571.prf .fairchildsemi. Truth Table Inputs CP X CLR H L L X: Don’t Care Outputs QA L QB L QC L QD...